A new A/D converter design. Bitblock converters.  

Update: After a discussion on a newsgroup I realized that this idea is not totally new.
It has been used in various A/D converters in the previous decades. I'll keep it
on my website however since I belive it's still a good description of a lesser known A/D conversion
technique.
Also available in PDF version IntroductionThis paper presents a new analog to digital converter implementation. The technique described here based on the wellknown process to convert base10 fractional numbers between 0 and 1 to their base2 representation. Different configurations featuring different speed, complexity and accuracy will be introduced. Converters with continuous time analog domain and logarithmic output will also presented. In the past various different methods has been invented to covert analog values to their digital representation. Devices used various electric or mathematic approaches to convert an analog voltage or current value to their digital representation. The class of converters introduced in this paper use a mathematical approach. All share one common central idea: a building block, that produces one bit of digital information (or in one variant one digit of information) at a time. Using this building block many different configurations can be constructed, with different trade offs in speed, complexity and accuracy. I will describe a configuration which can achieve comparable speed to successive approximation converters with constant complexity (i.e. the complexity of the converter is independent of the resolution). I will also describe a converter that performs comparable to (pipelined) flash converters with log_{2}(n) complexity (the complexity is proportional to the number of output bits, not the number of output values). Further modifications of the basic idea lead to a continuoustime A/D converter where the sampling occurs in the digital domain, and to a converter that performs logarithmic conversion. The basic ideaIt is a wellknown technique to convert fractional base10 numbers between 0 and 1 into their base2 representation. I will first describe it shortly just for completeness: Let's have a number N_{1} between 0 inclusive and 1 exclusive in it's base10 representation. We need it's base2 digits. It's first digit is off course 0 and than comes the fractional sign, '.'. The first digit after the fractional sign is '1' if N_{1} >= 0.5 and '0' otherwise. Lets subtract 0.5 from N_{1} if it is greater than 0.5, and multiply this by 2. This way we get a new number, N_{2} between 0 and 1 just as N_{1} was. It's first digit after the fractional sign is the second of N_{1,} so we can deduce N_{1} 's second digit with the same method only use N_{2} instead of N_{1}. We can continue this method until we reach N_{i} equals to 0 in which case all other digits are zeros, or we reach the desired accuracy. In formal:
An example:
So the first 6 digits of 0.41 in base2 is 0.011010. The main point is that we didn't need much knowledge about the source representation. We didn't actually use that the source representation was base10. We didn't even use that the representation is a number. What we did use is a method to decide weather a value is greater than 0.5 or not, a method to multiply a value by two, and a method to decrease a value by 1 if desired. If these functions available in any source representation, we can do the conversion. All described functionality is available in the analog domain so there is a possibility to design a circuit that implements the above algorithm. This construct will be introduced in the next chapter. The basic circuitryThe core of the algorithm described in the previous chapter is point 2. It can be considered as a black box, with one analog input (N_{i}), one analog output (N_{i+1}) and one digital output (O_{i}). For easier reference lets rename these signals as follows:
We have the transfer functions also defined: DOUT = (AIN>0.5)?1:0 AOUT = 2*AIN  DOUT We can construct a plot for these functions:
And we can easily create a circuit that can implement those transfer functions:
In this design the operational amplifiers considered to be ideal except that their output saturates to the power lines. One possible interpretation of this circuit is a 1bit A/D converter with a conversion error output amplified to fullscale. Lets call this building block as bitblock. Next, we will use this block in larger constructs, so it is practical to have a symbol represent of the above circuit:
We will also need a special track and hold circuit (a sample and hold circuit in its strict sense). Traditional T/H devices have two states. In state one (track) the input theoretically equals with the output. In state two (hold) the output equals the last input value of the track state. We will need a different behavior. The output should change only on state 12 transition and should keep it's value constant in both state one and two. The simplest implementation of this could be to cascade two traditional track and hold devices with inverted control input:
In the following figures this symbol will refer to the above circuit:
With these components at hand we can now construct the complete circuit that implements the described algorithm thus reassembling an A/D converter. Actually we can construct at least three basic structures. In the first case we use the strict algorithm definition above:
This circuit will work as an MSB first serial A/D converter. The analog input of the converter is In. The converter produces one bit on the output (Sout) for each clock pulse on Clk. The conversion starts with a oneclock wide pulse on the Start pin. The switch is shown in the position when Start is not active. This converter type provides more or less the same features for the outside world as a serial output successive approximation converter. Note however that the converter's complexity is independent of the precision of the conversion. One consequence of this feature is that the precision (the number of bits per sample) can be adjusted by control only and the same device can be used as an 8bit or a 12bit converter for example. If we unfold the loop of the algorithm and implement each iteration with a unique set of components we get another layout:
This circuit will provide a parallel output value on D[0..3] of each pulse on Clk. This output will be the converted value of In four clock cycles before. Naturally the circuit can be expanded to any number of bits. This circuit reassembles a pipeline A/D converter scheme. The complexity of the converter however is proportional to the number of output bits – except for the digital delay line which has a cubic complexity over the number of output bits  as opposed to the number of output values as in conventional flashconverters. If we sacrifice some performance for simplicity we can leave most of the sample and hold circuits and D filpflops out of the design. This will lead us to the third A/D converter implementation:
This converter scheme will produce one set of digital output on D[0..3] for each clock pulse on Clk. The output will correspond to the analog value on In at the time of last clock pulse. Thus this converter behaves like a flash converter with no pipelining effect. Performance considerationsDesign A has the unique feature to produce as many bits as desired. It also produces direct serial output, compatible with many current DSP's serial port. It can be used with such intelligent devices with nearly no additional logic. It's maximal conversion speed determined by the delay of the bitblock and the settling time of the sample and hold circuit. Of course it is also determined by the number of required bits: T_{min}= n * (T_{bb}+T_{sh}), where n is the number of output bits per sample, T_{bb} is the delay of the bitblock and T_{sh} is the settling time of the S/H circuit. It's minimal conversion speed is determined by the required precision and the fall of the output of the S/H circuit. The circuit's precision affected by the precision of the bitblock and the precision of the S/H circuits used. Design B's speed is determined by the delay of the bitblock and the settling time of the S/H circuit. Digital delay lines will probably be much faster than S/Hs so their delay isn't a factor. T_{min}= T_{bb}+T_{sh} This converter will perform a complete conversion under this time, so it's n times faster than design A. The minimal conversion time is determined by the same featured as design A but it also dependent on the output word length (the number of cascaded S/H circuits). This means that this converter cannot be used at such slow conversion rates as design A. It's precision is affected by the precision of the bitblock and the S/H circuits, but also depends upon the similarity of the many bitblocks and S/H's used. Design C has a maximum conversion speed between design A and B. It's conversion time is basically determined by the sum of the delay of the bitblock: T_{min}= n * T_{bb}+T_{sh} It's minimal conversion time is equal to design A because both determined by the falltime of the sample and hold circuit. The precision of this implementation is a function of the precision of one S/H circuit only and the precision and similarity of the bitblocks. As a result it's precision is also between design A and B. We can summarize the main features in the following table:
DerivativesDirect basen convertersAs mentioned earlier the bitblock can be considered as a onebit A/D converter with an amplified conversion error output. Having this in mind one can generalize the bitblock to other than base2 converters:
The resistor values R1 and R2 can be calculated from the criteria that AOUT's span must be equal to AIN's span. Naturally the digital output DOUT now consists of more than 1 wires. You can use this bitblock in any of the three basic designs. One benefit is that you convert more than one bit in one step. Another feature is that you are not tied to base2 any longer. You can create for example a decadic flash converter at the A/D convert stage of the bitblock (9 comparators) and thus getting direct base10 (for example BCD coded) output. As an example, let's see the transfer functions of a base3 bitblock:
Continuoustime convertersWith further modification of the transfer function of the bitblocks we can construct a converter that can have a continuoustime analog and a discretetime digital domain. To achieve this, we need to use a special coding of numbers, called Graycodes. The coding has the feature that neighboring codes differ only in one digit. This code is widely used in places where asynchronous signals have to be sampled in a synchronous part of the system, like in positional encoders or signals crossing clockdomains. A Graycoded number can be easily created from it's base2 representation: If a bit is one than invert all lower bits of the number. Starting from the MSB bit and applying the previous modification to all bits downwards one can get the Graycoded version of the original number. A small modification to the transfer characteristics of the bitblock can give us the same results:
Note, that the modified scheme does the same thing. If the bitblock's digital output is one, the analog output and thus all lower bits are inverted. Also, the analog output's transfer function became continuous. This is another implementation of the main idea behind Graycode, that is, a little change in the represented value causes a little change in the bits coding that value. A possible implementation using ideal, but saturating operational amplifiers (same as before) would be like this:
Using this modified bitblock, you can leave out even the last S/H circuit from converter design C. This will give us a continuoustime A/D converter, whose output can be sampled in the digital domain:
The main benefit of this layout is that digital domain sampling is much easier to do and much more accurate than the a S/H circuit can be. Further more this design is able to work on any low conversion frequencies which none of the previous designs could do. There is also a possibility to create "semi Graycoded" basen converters using the same technique. However in this case the base (n) should be an even number. For example a base4 output converter's semi Graycoded version would have the following transfer functions:
Naturally DOUT now should be Graycoded too. Logarithmic convertersUntil now we've used the same bitblock for generating all digits of the converted number. If we use different bitblocks at different bitpositions we can create converters with other than linear transfer functions. For example we can construct a directlogarithmic A/D converter. In the following this technique will be introduced with a 3bit logarithmic converter which can convert an input value from 1mV (inclusive) to 256mV (exclusive). The output will be log_{2}(In/[mV]) in our example. For a three bit converter the output values will correspond to the following input ranges:
For the following explanation it's convenient to extend the input range of our converter to include the upper bound also, in our case 256mV. For the extended input range the converter's theoretical transfer characteristic should be like this:
The most significant bit changes it's state at 16. This means that the MSB bit's bitblock's transfer functions should look like this:
Note that, the AINAOUT transfer function has two different slope parts. It complicates a bit the implementation of the bitblock, but it is still possible. It also can be noticed that it maps range 116 and range 16256 into the same output range (16256). The second bit changes it's state at values 1, 4, 16, 64 in the original input. But we want to connect this bit's bitblock over the MSB's bitblock which has the previously described mapping behavior. In detail it maps 1 to 1, 4 to 32, 16 to 1, 64 to 32. The two 0to1 transitions are mapped to the same value (32) and 1to0 transitions are also mapped to either 16 or 256. Now, we can construct the bitblock transfer functions for this bit:
As can be seen these transfer functions are not the same as the previous ones. The third bit changes it's state at every integral power of two. You can check that the first and the second bitblocks together maps all 1to0 transitions to 128 and all 0to1 transitions to either 64 or 256. The transfer functions can be designed as follows:
Having these bitblocks you can construct the complete 3bit direct logarithmic A/D converter. You only have to choose the proper configuration. Because the bitblocks are different it calls for design B or C where each bit has it's own dedicated bitblock. There's one important note to make here: the input span (along with the output span) of each stage decreases and though the upper bound remains the same the lower bound increases. As a summary here are the general equations to implement an nbit logarithmic A/D converter: Design inputs:
Design outputs:
ConclusionsThe basic idea explained at the beginning of this article can be the source of a group of A/D converters. They differ in complexity, speed and accuracy. They also differ in output code (Graycode, binary code, or basen code including BCD). Their interface can be serial or parallel and their transfer function can be linear or logarithmic. They can perform similar to existing converter classes with reduced complexity. Some has unique features, like direct logarithmic output, continuous time analog sampling or variable precision, not customary in current techniques. Future workEach of the building blocks and converter layouts should be tested against various realworld effects, like the nonideal behavior of the operational amplifiers, nonperfect resistor values, parasitic effects, etc. Because both design A, B and C are basically discrete time analog circuits it calls for a switched capacitor circuit implementation. 

© 2004 Andras Tantos 